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Rev 0; 6/07
KIT ATION EVALU E AILABL AV
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
General Description
The MAXQ3100 microcontroller is a low-power, 16-bit RISC device that incorporates an integrated liquid-crystal display (LCD) interface that can drive up to 160 segments, two analog comparators with precision internal 1.25V reference voltage, and a real-time clock (RTC) module with a dedicated battery-backup supply. An internal temperature sensor allows software to monitor device temperature and optionally interrupt to alert when a temperature conversion is complete. The MAXQ3100 is uniquely suited for single-phase electricity metering applications that require an external analog front-end, but can be used in any application that requires high-performance operation. The device operates at a fixed 4.194MHz, generated from the 32.76kHz RTC crystal. The device has 8kWords of EEPROM, 512 words of RAM, three 16-bit timers, and two universal synchronous/asynchronous receiver/transmitters (USARTs). The microcontroller core and I/O are powered by a single 3.3V supply, and an additional battery supply keeps the RTC running during power outages.
Features
High-Performance, Low-Power, 16-Bit RISC Core 4.194MHz Operation, Approaching 1MIPS per MHz 3.3V Core and I/O 33 Instructions, Most Single-Cycle Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/ Decrement 16-Level Hardware Stack 16-Bit Instruction Word, 16-Bit Data Bus 16 x 16-Bit, General-Purpose Working Registers Optimized for C-Compiler (High-Speed/Density Code) Program and Data Memory 8kWords EEPROM 200,000 EEPROM Write/Erase Cycles 512 Words of Internal Data RAM JTAG-Compatible Debug Port Bootloader for Programming Peripheral Features Up to 27 General-Purpose I/O Pins, Most 5V Tolerant 160-Segment LCD Driver Up to 4 COM and 40 Segments Static, 1/2, and 1/3 LCD Bias Supported No External Resistors Required Two Analog Comparators with Internal +1.25V Precision Reference Two Serial USARTs, One with Infrared PWM Support Digital Temperature Sensor Three 16-Bit Programmable Timers/Counters 8-Bit, Subsecond, System Timer/Alarm Battery-Backed, 32-Bit RTC with Time-of-Day Alarm and Digital Trim Programmable Watchdog Timer Flexible Programming Interface Bootloader Simplifies Programming In-System Programming Through Debug Port Supports In-Application Programming of EEPROM Power Consumption 1.9mA at 4.194MHz, 3.6V Operation 1.9A Standby Current in Sleep Mode Low-Power Divide-by-256 Mode
1
MAXQ3100
Applications
Utility Meters Battery-Powered and Portable Devices Electrochemical and Optical Sensors Industrial Control Data-Acquisition Systems and Data Loggers Home Appliances Consumer Electronics Thermostats/Humidity Sensors Security Sensors Gas and Chemical Sensors HVAC Smart Transmitters
Ordering Information
PART MAXQ3100-EMN+ TEMP RANGE -40C to +85C PIN-PACKAGE 80 MQFP
+Denotes a Pb-free/RoHS-compliant device.
Typical Application Circuits and Pin Configuration appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
ABSOLUTE MAXIMUM RATINGS
Voltage Range on DVDD Relative to DGND ..........-0.5V to +6.0V Voltage Range on Any Pin Relative to DGND (3V Tolerant) .........................................-0.5V to (DVDD + 0.5V) Continuous Output Current (Any Single I/O Pin)..........................................................25mA (All I/O Pins Combined) ...................................................25mA Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Soldering Temperature .......................................See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD = VRST to 3.6V, f32KIN = 32.768kHz, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Digital Supply Voltage Digital Power-Fail Reset Battery Supply Voltage SYMBOL DVDD VRST VBAT IDD1 Active Current (Note 2) IDD2 IDD3 IDD4 IDD5 /1 mode /2 mode /4 mode /8 mode PMM1 mode Brownout detector disabled (Note 3), TA = +25C I STOP1 Stop-Mode Current Brownout detector disabled (Note 3), TA = +60C Brownout detector disabled (Note 3), TA = +85C I STOP2 I STOP3 ANALOG VOLTAGE COMPARATOR Comparator Input-Voltage Range Internal Voltage Reference Input Offset Voltage Input Common-Mode Voltage Common-Mode Rejection Ratio DC Input-Leakage Current Comparator Setup Time Response Time (CMPx Change to CMO Valid) Current Consumed By Comparator VINPUT VREF VOS VCMR CMMR (Note 4) (Note 4) (Note 4) TA = +25C, CMPx pin in tri-state mode tCMP_SETUP f SYS = 4.194MHz, V = 20mV (Note 4) tCMP_RESP f SYS = 4.194MHz, transition CMPx from DGND to DVDD in ~2ns, tSYS = 1/f SYS (Note 4) Per enabled comparator, CMONx = 1, brownout detector enabled, CMPx pins in tri-state mode GND 1.15 -10 1 55 -50 0.8 140 + (2 x t SYS) 18.0 +50 1.6 600 + (2 x t SYS) 39.0 1.25 DVDD 1.35 +10 DVDD V V mV V dB nA s ns Brownout detector enabled (Note 3) Brownout detector enabled, RTC enabled (Note 3) CONDITIONS MIN VRST 2.34 2.0 1.9 1.3 1.0 0.8 0.7 1.9 2.1 3.3 16.3 16.4 TYP 3.3 2.5 MAX 3.6 2.71 3.8 2.6 1.8 1.4 1.2 1.0 5.0 10.0 A 35.0 63.0 64.0 mA UNITS V V V
IDD_CMP
A
2
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = VRST to 3.6V, f32KIN = 32.768kHz, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER DIGITAL I/O Input High Voltage (Port 0, 1, 3, RESET) Input High Voltage (Port 2) Input Low Voltage Output High Voltage (All Ports) Output Low Voltage (All Ports, RESET) Input Pullup Current Input Leakage (All Ports) TEMPERATURE SENSOR 10-bit resolution, f SYS = 4.194MHz Temperature Conversion Time TCONV 11-bit resolution, f SYS = 4.194MHz 12-bit resolution, f SYS = 4.194MHz 13-bit resolution, f SYS = 4.194MHz Temperature Sensor Accuracy RTC Battery Supply Current, BatteryBacked Mode Battery Supply Leakage Current Trimming Resolution LCD LCD Supply Voltage LCD Bias Voltage 1 LCD Bias Voltage 2 LCD Adjustment Voltage VLCD VLCD1 VLCD2 VADJ (Note 4) (Note 4) (Note 4) Measured on DVDD pin; LCFG = 0xF7, LCRA = 0x1B20, LCDx = 0xFF; LCD pins are unconnected LRA3:LRA0 = 1111 2.4 VADJ + 2/3 (VLCD - VADJ) VADJ + 1/3 (VLCD - VADJ) 0 0.4 x VLCD 0.1 40 80 DVDD V V V V IBAT IBATL Measured on VBAT pin, VBAT = 3.6V, DVDD = 0V, RTC enabled Measured on VBAT pin, VBAT = 3.6V, DVDD = 3.6V, RTC enabled One 32.768kHz clock per 10s (Note 4) 3.05 1.76 4 3.1 200 A nA ppm 12.5 25 50 100 2 C ms VIH1 VIH2 VIL VOH VOL I PULLUP IL I SOURCE = 3mA I SINK = 4mA DVDD = 3.6V, input mode with weak pullup enabled Input mode with weak pullup disabled 40 -50 120 DVDD 0.4 0.8 x DVDD 0.8 x DVDD 5.5 DVDD + 0.3 0.2 x DVDD DVDD 0.4 250 +50 V V V V V A nA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAXQ3100
LCD Digital Operating Current LCD Bias Resistor LCD Adjust Resistor
ILCD RLCD RLADJ
A k k
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = VRST to 3.6V, f32KIN = 32.768kHz, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS Segment is driven at VLCD; VLCD = 3V, I SEGxx = -3A, guaranteed by design Segment is driven at VLCD1; VLCD1 = 2V, I SEGxx = -3A, guaranteed by design Segment is driven at VLCD2; VLCD2 = 1V, I SEGxx = -3A, guaranteed by design Segment is driven at VADJ; VADJ = 0V, I SEGxx = +3A, guaranteed by design CLOCK SOURCES External Crystal Frequency Internal Clock Frequency System Clock Frequency JTAG-COMPATIBLE PROGRAMMING TCK Frequency MEMORY CHARACTERISTICS EEPROM Write/Erase Cycles EEPROM Data Retention Theta-JA = +25C Theta-JA = +85C Theta-JA = +85C 200,000 50,000 50 Cycles Years fTCK JTAG programming (Note 4) 0 f SYS / 8 MHz f32KIN fCLK f SYS f32KIN = 32.768kHz, DVDD = 3.6V f SYS = fCLK / system clock divisor 4.110 fCLK / 256 32.768 4.194 4.278 fCLK kHz MHz MIN VLCD 0.06 VLCD1 0.04 VLCD2 0.02 VADJ TYP MAX VLCD VLCD1 V VLCD2 0.1 UNITS
LCD Segment Voltage
VSEGxx
Note 1: Note 2: Note 3: Note 4:
Specifications to -40C are guaranteed by design and are not production tested. Measured on the DVDD pin with DVDD = 3.6V, VBAT = 3.8V, f32KIN = 32.768kHz, executing from EEPROM. Measured on the DVDD pin with DVDD = 3.6V, VBAT = 3.8V, f32KIN = 32.768kHz, all I/O pins disconnected, and not in reset. Specification guaranteed by design but not production tested.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Pin Description
PIN 1, 11, 52, 58, 75 6, 53, 59, 76 NAME DGND DVDD Digital Ground Digital Supply Voltage (+3.3V) General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins only. All port pins default to input mode with weak pullups enabled after a reset. All port pins can be configured as external interrupt inputs. All alternate functions must be enabled from software. PIN P0.0-P0.7; INT0-INT7; TXD0, RXD0, T0G, T0, T1, EX 77 78 79 80 2 3 4 5 7-10 12-43 COM0-COM3 SEG1-SEG31 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 NAME INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 SPECIAL/ALTERNATE FUNCTION NAME TXD0 RXD0 T0G T0 T1 T1EX -- -- FUNCTION Serial Port 0 Transmit Serial Port 0 Receive Timer 0 Gate Input Timer 0 Input Timer 1 Input/Output Timer 1 External Capture/Reload Input -- -- FUNCTION
MAXQ3100
2-5, 77-80
Dedicated LCD Common-Voltage Outputs Dedicated LCD Drive Outputs General-Purpose, Digital, I/O, Type C Port; LCD Segment-Driver Output. These port pins function as bidirectional I/O pins and LCD segment-driver outputs. All alternate functions must be enabled from software. PIN 44 NAME P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SPECIAL/ALTERNATE FUNCTION NAME SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 FUNCTION LCD Segment 32 LCD Segment 33 LCD Segment 34 LCD Segment 35 LCD Segment 36 LCD Segment 37 LCD Segment 38 LCD Segment 39
44-51
P2.0-P2.7; SEG32-SEG39
45 46 47 48 49 50 51
54
VLCD
LCD Bias-Control Voltage. Highest LCD drive voltage used in all bias modes. This pin must be connected to an external supply when using the LCD display controller. LCD Bias, Voltage 1. Next highest LCD drive voltage, used in 1/2 and 1/3 LCD bias modes. An internal resistor-divider sets the voltage at this pin. External resistors and capacitors can be used to change LCD voltage or drive capability at this pin. This pin must be shunted externally to VLCD2 when using 1/2 bias mode.
55
VLCD1
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Pin Description (continued)
PIN NAME FUNCTION LCD Bias, Voltage 2. Third highest LCD drive voltage, used in 1/3 LCD bias mode only. An internal resistor-divider sets the voltage at this pin. External resistors and capacitors can be used to change LCD voltage or drive capability at this pin. This pin must be shunted externally to VLCD1 when using 1/2 bias mode. LCD Adjustment Voltage. Lowest LCD drive voltage, used in all bias modes. Connect to DGND through an external resistor to provide external control of the LCD contrast. Leave disconnected for internal contrast adjustment. General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins only. All port pins default to input mode with weak pullups enabled after a reset. Port pins P1.0-P1.3 can be configured as external interrupt inputs. All alternate functions must be enabled from software. 60-63 P1.0-P1.3; INT8-INT11; T2B, T2A, TXD1, RXD1 PIN 60 61 62 63 P1.0 P1.1 P1.2 P1.3 NAME INT8 INT9 INT10 INT11 SPECIAL/ALTERNATE FUNCTION NAME T2B T2A TXD1 RXD1 FUNCTION Timer 2 Secondary I/O Timer 2 Primary I/O Serial Port 1 Transmit Serial Port 1 Receive
56
VLCD2
57
VADJ
General-Purpose, Digital, I/O, Type C Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins only. All port pins default to input mode with weak pullups enabled after a reset. All alternate functions must be enabled from software, except for the JTAG-compatible functions that are enabled by default following reset. PIN 64-70 P3.0-P3.6; TDI, TDO, TCK, TMS, SWQ, CMP0, CMP1 64 65 66 67 68 69 70 71 RESET NAME P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 SPECIAL/ALTERNATE FUNCTION NAME TDI TDO TCK TMS SQW CMP0 CMP1 FUNCTION JTAG TAP Data Input JTAG TAP Data Output JTAG TAP Clock Input JTAG TAP Mode-Select Input RTC Square-Wave Output Analog Comparator Input 0 Analog Comarator Input 1
72 73 74
VBAT 32KIN 32KOUT
Active-Low, Digital Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin must be pulled high by an external 50k resistor. This pin is driven low as an output when an internal reset condition occurs. Digital Battery-Backup Supply. This supply provides an optional battery backup for the RTC when DVDD power is removed. If this pin is connected to a nominal 3.3V battery then the RTC will operate and battery-backed register contents will be preserved when DVDD is removed. If battery backup is not required this pin should be connected directly to DVDD. 32kHz Crystal Input/Output. Connect an external, 6pF 32kHz watch crystal between 32KIN and 32KOUT to generate the system clock.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Functional Diagram
MAXQ3100
TIMER 0-TYPE 16-BIT TIMER/COUNTER ANALOG COMPARATOR 8kW EEPROM (PROGRAM) +1.25V REFERENCE TIMER 1-TYPE 16-BIT TIMER/COUNTER
512W SRAM (DATA)
TIMER 2-TYPE 16-BIT TIMER/COUNTER
ANALOG COMPARATOR
2kW UTILITY ROM SERIAL USART
160-SEGMENT LCD DRIVER
MAXQ3100
MAXQ20 RISC CORE
(16 x 16-BIT ACCUMULATORS)
SERIAL USART WITH INFRARED PWM SUPPORT
REAL-TIME CLOCK WATCHDOG TIMER DIGITAL TEMPERATURE SENSOR EXTERNAL 32.768kHz CRYSTAL POWER REDUCTION/ CLOCK GENERATION
3.3V
POR
JTAG
TMS TDI TDO TCK
Detailed Description
The following is an introduction to the primary features of the microcontroller. More detailed descriptions of the device features can be found in the data sheets, errata sheets, and user's guides described later in the Additional Documentation section.
MAXQ Core Architecture
The MAXQ3100 is a high-performance, CMOS, 16-bit RISC microcontroller with EEPROM and an integrated 160-segment LCD controller. It is structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, because the instruction
contains both the op code and data. The result is a streamlined 4.194 million instructions-per-second (MIPS) microcontroller. The highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. As a result, the application speed is greatly increased.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Instruction Set
The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special-function registers control the peripherals and are subdivided into register modules. The family architecture is modular, so that new devices and modules can reuse code developed for existing products. The architecture is transport-triggered. This means that writes or reads from certain register locations can also cause side effects to occur. These side effects form the basis for the higher-level op codes defined by the assembler, such as ADDC, OR, JUMP, etc. The op codes are actually implemented as MOVE instructions between certain system register locations, while the assembler handles the encoding, which need not be a concern to the programmer. The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of the instruction. Bits 0 to 7 of the instruction represent the source for the transfer. Depending on the value of the format field, this can either be an immediate value or a source register. If this field represents a register, the lower four bits contain the module specifier and the upper four bits contain the register index in that module. Bits 8 to 14 represent the destination for the transfer. This value always represents a destination register, with the lower four bits containing the module specifier and the upper three bits containing the register subindex within that module. Anytime that it is necessary to directly select one of the upper 24 index locations in a destination module, the prefix register PFX is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. data memory. The configuration of program and data space depends on the current execution location. * When executing code from EEPROM memory, the SRAM and utility ROM are accessible in data space. * When executing code from SRAM, the EEPROM and utility ROM are accessible in data space. * When executing code from the utility ROM, the EEPROM memory and SRAM are accessible in data space. Refer to the MAXQ Family User's Guide: MAXQ3100 Supplement for more details. In all cases, whichever memory segment is currently being executed from cannot be accessed in data space. To allow the use of lookup tables and similar constructs in the memory, the utility ROM contains a set of lookup and block copy routines (refer to the user's guide supplement for more details). The incorporation of EEPROM allows the device to be reprogrammed, eliminating the expense of throwing away one-time programmable devices during development and field upgrades. Program memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals.
Stack Memory
A 16-bit-wide internal stack provides storage for program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The stack can also be used explicitly to store and retrieve data by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the stack location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at the stack location pointed to by SP, and then decrement SP.
Memory Organization
The device incorporates several memory areas: * 2kWords utility ROM * 8kWords of EEPROM for program storage * 512 words of SRAM for storage of temporary variables * 16-level, 16-bit-wide stack memory for storage of program return addresses and general-purpose use The memory is arranged by default in a Harvard architecture, with separate address spaces for program and
Utility ROM
The utility ROM is a 2kWord block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include: * In-system programming (bootloader) over the JTAGcompatible debug port * In-circuit debug routines * User-callable routines for in-application flash programming and code space table lookup
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
PROGRAM SPACE DATA SPACE (BYTE MODE) DATA SPACE (WORD MODE)
512 x 16 DATA SRAM
A1FFh A000h
87FFh 2k x 16 UTILITY ROM 8000h 4k x 8 UTILITY ROM
8FFFh 2k x 16 UTILITY ROM 8000h
87FFh
8000h
1FFFh
EXECUTING FROM
8k x 16 PROGRAM EEPROM 1k x 8 DATA SRAM 03FFh 0000h 512 x 16 DATA SRAM 01FFh 0000h
0000h
Figure 1. Memory Map When Executing from EEPROM
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to the start of user-application code (located at address 0000h), or to the bootloader. Routines within the utility ROM are useraccessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the user's guide supplement for this device. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. A single password-lock (PWL) bit is implemented in the SC register. When the PWL is set to one (power-on reset default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase.
MAXQ3100
Activating the debug port and loading the test access port (TAP) with the system programming instruction invokes the bootloader. Setting the SPE bit to 1 during reset through the debug port executes the bootloadermode program that resides in the utility ROM. When programming is complete, the bootloader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootloader functions are supported: * * * * * Load Dump CRC Verify Erase
Programming
The microcontroller's EEPROM can be programmed by two different methods: in-system programming and inapplication programming. Both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. In-system programming can be password protected to prevent unauthorized access to code memory.
In-Application Programming The in-application programming feature allows the microcontroller to modify its own program memory from its application software. This allows on-the-fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible programming functions that erase and program memory. These functions are described in detail in the user's guide supplement for this device.
Register Set
Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that may be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. Tables 1 and 4 show the MAXQ3100 register set.
In-System Programming An internal bootloader allows the device to be reloaded over a simple JTAG-compatible debug port. As a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another microcontroller, or a connection to a PC serial port using a serial-to-JTAG converter such as the one included in the MAXQ3100 evaluation kit. If in-system programmability is not required, a commercial gang programmer can be used for mass programming.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Table 1. System Register Map
MODULE NAME (BASE SPECIFIER) REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh AP (8h) AP APC -- -- PSF IC IMR -- SC -- -- IIR -- -- CKCN WDCN A (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] PFX (Bh) PFX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IP (Ch) IP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SP (Dh) -- SP IV -- -- -- LC[0] LC[1] -- -- -- -- -- -- -- -- DPC (Eh) -- -- -- Offs DPC GR GRL BP GRS GRH GRXL BP[offs] -- -- -- -- DP (Fh) -- -- -- DP[0] -- -- -- DP[1] -- -- -- -- -- -- -- --
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. Registers in module AP are bit addressable.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Table 2. System Register Bit Functions
REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A[0..15] PFX IP SP IV LC[0] LC[1] Offs DPC GR GRL BP GRS GRH GRXL BP[offs] DP[0] DP[1] GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0 -- -- -- -- -- -- -- -- -- GR (16 bits) GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.9 GR.9 GR.1 GR.0 GR.8 GR.8 GR.0 BP (16 bits) GR.15 GR.14 GR.15 GR.14 GR.7 GR.6 BP[offs] (16 bits) DP[0] (16 bits) DP[1] (16 bits) GR.13 GR.12 GR.11 GR.10 GR.13 GR.12 GR.11 GR.10 GR.5 GR.4 GR.3 GR.2 -- -- -- -- -- -- -- -- -- -- REGISTER BIT 15 14 13 12 11 10 9 8 7 -- CLR Z -- IMS TAP IIS -- POR A[n] (16 bits) PFX (16 bits) IP (16 bits) -- IV (16 bits) LC[0] (16 bits) LC[1] (16 bits) Offs (8 bits) WBS2 WBS1 WBS0 SDPS1 SDPS0 -- -- -- SP (4 bits) 6 -- IDS S -- -- -- -- -- EWDI 5 -- -- -- CGDS -- -- -- -- WD1 4 -- -- GPF1 -- -- -- -- STOP WD0 -- GPF0 -- IM3 -- II3 SWB WDIF 3 2 MOD2 OV -- -- -- -- PMME WTRF 1 MOD1 C INS IM1 PWL II1 CD1 EWT 0 MOD0 E IGE IM0 -- II0 CD0 RWT AP (4 bits)
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Table 3. System Register Reset Values
REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A[0..15] PFX IP SP IV LC[0] LC[1] Offs DPC GR GRL BP GRS GRH GRXL BP[offs] DP[0] DP[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 0 0 1 0 0 1 0 1 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 s 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 s 0 0 s 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: Bits marked with an "s" have special behavior upon reset. Refer to the user's guide supplement for this device for more details.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Table 4. Peripheral Register Map
REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh M0 (0h) PO0 SCON0 SBUF0 T0CN T0L T1CN T1MD EIF0 PI0 SMD0 PR0 T0H T1L T1H T1CL T1CH PD0 -- -- -- -- -- -- -- -- -- -- -- -- -- EIE0 EIES0 M1 (1h) PO1 SCON1 SBUF1 T2CNB T2H T2RH T2CH EIF1 PI1 SMD1 PR1 T2CNA T2CFG T2V T2C IRCN PD1 T2R -- -- -- -- -- -- -- -- -- -- -- -- EIE1 EIES1 M2 (2h) PO2 LCFG LCRA LCD0 LCD1 LCD2 LCD3 LCD4 PI2 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 PD2 LCD12 LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19 -- -- -- -- -- -- -- M3 (3h) PO3 RTRM RCNT CCN0 CCN1 -- TEMPR TPCFG PI3 RTSS RTSH RTSL RSSA RASH RASL PWCN PD3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide.
14
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Table 5. Peripheral Register Bit Functions
REGISTER BIT 13 PO0.7 SM0/FE SBUF0.7 ET0 T0L.7 TF1 -- IE7 PI0.7 EIR PR0.9 T0H.7 T1L.7 T1H.7 T1CL.7 PD0.7 EX7 IT7 -- SM0/FE SBUF1.7 ET2L T2V.15 T2R.15 T2C.15 -- -- -- PR1.9 PR1.8 PR1.7 -- SM1 IT6 EX6 PD0.6 PD0.5 EX5 IT5 -- SM2 T1CL.6 T1CL.5 T1H.6 T1H.5 T1H.4 T1CL.4 PD0.4 EX4 IT4 -- REN SBUF1.6 SBUF1.5 SBUF1.4 T2OE1 T2V.14 T2R.14 T2C.14 -- -- -- PR1.6 T2POL1 T2V.13 T2R.13 T2C.13 -- -- -- PR1.5 -- T2V.12 T2R.12 T2C.12 -- -- -- PR1.4 T1L.6 T1L.5 T1L.4 T0H.6 T0H.5 T0H.4 PR0.8 PR0.7 PR0.6 PR0.5 PR0.4 PR0.3 T0H.3 T1L.3 T1H.3 T1CL.3 PD0.3 EX3 IT3 PO1.3 TB8 SBUF1.3 TF2 T2V.11 T2R.11 T2C.11 IE11 PI1.3 -- PR1.3 OFS -- -- -- PI0.6 PI0.5 PI0.4 PI0.3 PI0.2 ESI PR0.2 T0H.2 T1L.2 T1H.2 T1CL.2 PD0.2 EX2 IT2 PO1.2 RB8 IE6 IE5 IE4 IE3 IE2 -- -- -- -- -- ET1 IE1 PI0.1 SMOD PR0.1 T0H.1 T1L.1 T1H.1 T1CL.1 PD0.1 EX1 IT1 PO1.1 TI EXF1 T1OE DCEN EXEN1 TR1 C/T1 T0L.6 T0L.5 T0L.4 T0L.3 T0L.2 T0L.1 T0M TF0 TR0 GATE C/T M1 M0 T0L.0 CP/RL1 T1M IE0 PI0.0 FEDE PR0.0 T0H.0 T1L.0 T1H.0 T1CL.0 PD0.0 EX0 IT0 PO1.0 RI SBUF1.2 SBUF1.1 SBUF1.0 TF2L T2V.10 T2R.10 T2C.10 IE10 PI1.2 ESI PR1.2 TCC2 T2V.9 T2R.9 T2C.9 IE9 PI1.1 SMOD PR1.1 TC2L T2V.8 T2R.8 T2C.8 IE8 PI1.0 FEDE PR1.0 SBUF0.6 SBUF0.5 SBUF0.4 SBUF0.3 SBUF0.2 SBUF0.1 SBUF0.0 SM1 SM2 REN TB8 RB8 TI RI PO0.6 PO0.5 PO0.4 PO0.3 PO0.2 PO0.1 PO0.0 12 11 10 9 8 7 6 5 4 3 2 1 0
REGISTER
15
14
PO0
SCON0
SBUF0
T0CN
T0L
T1CN
T1MD
EIF0
PI0
SMD0
PR0
PR0.15 PR0.14 PR0.13 PR0.12 PR0.11 PR0.10
T0H
T1L
T1H
T1CL
PD0
EIE0
EIES0
PO1
SCON1
SBUF1
T2CNB
T2H
T2RH
T2CH
EIF1
PI1
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
MAXQ3100
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SMD1
PR1
PR1.15 PR1.14 PR1.13 PR1.12 PR1.11 PR1.10
15
MAXQ3100
13 ET2 T2CI T2V.13 T2C.13 -- -- T2R.13 -- -- PO2.7 PCF3 -- LCD0.7 LCD1.7 LCD2.7 LCD3.7 LCD4.7 PI2.7 LCD5.7 LCD6.7 LCD7.7 LCD8.7 LCD9.7 LCD5.6 LCD6.6 LCD7.6 LCD8.6 LCD9.6 PI2.6 LCD4.6 LCD4.5 PI2.5 LCD5.5 LCD6.5 LCD7.5 LCD8.5 LCD9.5 LCD3.6 LCD3.5 LCD2.6 LCD2.5 LCD2.4 LCD3.4 LCD4.4 PI2.4 LCD5.4 LCD6.4 LCD7.4 LCD8.4 LCD9.4 LCD10.7 LCD10.6 LCD10.5 LCD10.4 LCD11.7 LCD11.6 LCD11.5 LCD11.4 PD2.7 PD2.6 PD2.5 PD2.4 LCD12.7 LCD12.6 LCD12.5 LCD12.4 LCD1.6 LCD1.5 LCD1.4 LCD0.6 LCD0.5 LCD0.4 DUTY1 DUTY0 FRM3 FRM2 FRM1 FRM0 -- LRIG -- LRA3 LCD0.3 LCD1.3 LCD2.3 LCD3.3 LCD4.3 PI2.3 LCD5.3 LCD6.3 LCD7.3 LCD8.3 LCD9.3 LCD10.3 LCD11.3 PD2.3 LCD12.3 PCF2 PCF1 PCF0 -- PO2.6 PO2.5 PO2.4 PO2.3 PO2.2 SMO LRA2 LCD0.2 LCD1.2 LCD2.2 LCD3.2 LCD4.2 PI2.2 LCD5.2 LCD6.2 LCD7.2 LCD8.2 LCD9.2 LCD10.2 LCD11.2 PD2.2 LCD12.2 -- -- -- IT11 IT10 -- -- -- EX11 EX10 T2R.12 T2R.11 T2R.10 T2R.9 T2R.8 T2R.7 T2R.6 T2R.5 T2R.4 T2R.3 T2R.2 T2R.1 EX9 IT9 PO2.1 OPM LRA1 LCD0.1 LCD1.1 LCD2.1 LCD3.1 LCD4.1 PI2.1 LCD5.1 LCD6.1 LCD7.1 LCD8.1 LCD9.1 -- -- -- PD1.3 PD1.2 PD1.1 -- -- -- -- IREN IRTX IRBB PD1.0 T2R.0 EX8 IT8 PO2.0 DPE LRA0 LCD0.0 LCD1.0 LCD2.0 LCD3.0 LCD4.0 PI2.0 LCD5.0 LCD6.0 LCD7.0 LCD8.0 LCD9.0 LCD10.1 LCD10.0 LCD11.1 LCD11.0 PD2.1 PD2.0 LCD12.1 LCD12.0 T2C.12 T2C.11 T2C.10 T2C.9 T2C.8 T2C.7 T2C.6 TCV.5 TCV.4 TCV.3 TCV.2 TCV.1 TCV.0 T2V.12 T2V.11 T2V.10 T2V.9 T2V.8 T2V.7 T2V.6 T2V.5 T2V.4 T2V.3 T2V.2 T2V.1 T2V.0 DIV2 DIV1 DIV0 T2MD CCF1 CCF0 C/T2 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 G2EN 12 11 10 9 8 REGISTER BIT 7 6 5 4 3 2 1 0
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
16
Table 5. Peripheral Register Bit Functions (continued)
REGISTER
15
14
T2CNA
T2CFG
T2V
T2V.15
T2V.14
T2C
T2C.15
T2C.14
IRCN
PD1
T2R
T2R.15
T2R.14
EIE1
EIES1
PO2
LCFG
LCRA
--
--
LCD0
LCD1
LCD2
LCD3
LCD4
PI2
LCD5
LCD6
LCD7
LCD8
LCD9
LCD10
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LCD11
PD2
LCD12
Table 5. Peripheral Register Bit Functions (continued)
13 LCD13.7 LCD13.6 LCD13.5 LCD14.7 LCD14.6 LCD14.5 LCD15.7 LCD15.6 LCD15.5 LCD16.7 LCD16.6 LCD16.5 LCD17.7 LCD17.6 LCD17.5 LCD18.7 LCD18.6 LCD18.5 LCD19.7 LCD19.6 LCD19.5 -- TSGN -- CMON CMON CMIE CMF CMM -- CMIE CMF CMM -- -- -- -- FT SQE ALSF ALDF RDYE RDY BUSY TRM6 TRM5 TRM4 TRM3 TRM2 ASE CMO CMO PO3.6 PO3.5 PO3.4 PO3.3 PO3.2 LCD19.4 LCD19.3 LCD19.2 LCD18.4 LCD18.3 LCD18.2 LCD17.4 LCD17.3 LCD17.2 LCD16.4 LCD16.3 LCD16.2 LCD16.1 LCD16.0 LCD17.1 LCD17.0 LCD18.1 LCD18.0 LCD19.1 LCD19.0 PO3.1 TRM1 ADE CMPOL CMPOL PO3.0 TRM0 RTCE -- -- LCD15.4 LCD15.3 LCD15.2 LCD15.1 LCD15.0 LCD14.4 LCD14.3 LCD14.2 LCD14.1 LCD14.0 LCD13.4 LCD13.3 LCD13.2 LCD13.1 LCD13.0 12 11 10 9 8 REGISTER BIT 7 6 5 4 3 2 1 0
REGISTER
15
14
LCD13
LCD14
LCD15
LCD16
LCD17
LCD18
LCD19
PO3
RTRM
RCNT
WE
--
CCN0
CCN1
TEMPR TPIF -- RTSS.7 RTSH. 13 RTSH.7 RSTL.7 RSSA.7 -- RASL. 13 RASL. 12 RASL. 11 RASL. 10 RASL. 9 RASL. 8 RASL.7 -- -- RTSL.6 RSSA.6 -- RASL.6 -- PD3.6 RTSH.6 RTSH. 12 RTSH. 11 RTSH. 10 RTSH. 9 RTSH. 8 RTSS.6 RTSS.5 RTSH.5 RTSL.5 RSSA.5 -- RASL.5 -- PD3.5 PI3.6 PI3.5 TPIE -- -- PI3.4 RTSS.4 RTSH.4 RTSL.4 RSSA.4 -- RASL.4 -- PD3.4
TEMPR TEMPR TEMPR TEMPR TEMPR TEMPR .15 .14 .13 .12 .11 .10
TEMPR TEMPR TEMPR.7 TEMPR.5 TEMPR.5 TEMPR.4 TEMPR.3 TEMPR.2 TEMPR.1 TEMPR.0 .9 .8 -- PI3.3 RTSS.3 RTSH.3 RTSL.3 RSSA.3 RASH.3 RASL.3 -- PD3.3 RES1 PI3.2 RTSS.2 RTSH.2 RTSL.2 RSSA.2 RASH.2 RASL.2 -- PD3.2 RES0 PI3.1 RTSS.1 RTSH.1 RTSL.1 RSSA.1 RASH.1 RASL.1 -- PD3.1 START PI3.0 RTSS.0 RTSH.0 RTSL.0 RSSA.0 RASH.0 RASL.0 BOD PD3.0
TPCFG
PI3
RTSS
RTSH
RTSH. 14
RTSL
RSSA
RTSH. 15 RTSL. 15 RSSA. 15 RTSL. 13 RSSA. 13 RTSL. 12 RSSA. 12 RTSL. 11 RSSA. 11 RTSL. 10 RSSA. 10 RTSL. 9 RSSA. 9 RTSL. 8 RSSA. 8
RSTL. 14 RSSA. 14
RASH
RASL
RASL. 15
RASL. 14
PWCN
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
MAXQ3100
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PD3
17
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Table 6. Peripheral Register Bit Reset Values
REGISTER PO0 SCON0 SBUF0 T0CN T0L T1CN T1MD EIF0 PI0 SMD0 PR0 T0H T1L T1H T1CL T1CH PD0 EIE0 EIES0 PO1 SCON1 SBUF1 T2CNB T2H T2RH T2CH EIF1 PI1 SMD1 PR1 T2CNA T2CFG T2V T2C IRCN PD1 T2R EIE1 EIES1 PO2 LCFG REGISTER BIT 15 14 13 12 11 10 9 8 7 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 6 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 5 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
0
Note: Bits marked with an "s" have special behavior upon reset. Refer to the user's guide supplement for this device for more details.
18
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Table 6. Peripheral Register Bit Reset Values (continued)
REGISTER LCRA LCD0 LCD1 LCD2 LCD3 LCD4 PI2 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 PD2 LCD12 LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19 PO3 RTRM RCNT CCN0 CCN1 TEMPR TPCFG PI3 RTSS RTSH RTSL RSSA RASH RASL PWCN PD3 REGISTER BIT 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s 0 0 s s s 0 0 0 0 0 6 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 s 0 s s s s 0 0 0 0 0 5 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s 0 0 0 s 0 s s s s 0 0 0 0 0 4 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s 0 0 0 s 0 s s s s 0 0 0 0 0 3 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s 1 0 0 s 0 s s s s 0 0 0 0 0 2 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s 0 0 0 s 0 s s s s 0 0 0 0 0 1 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s 0 0 0 s 0 s s s s 0 0 0 0 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s s 0 0 s 0 s s s s 0 0 0 s 0
s
s
s
s
s
s
s
s
s s 0 0
s s 0 0
s s 0 0
s s 0 0
s s 0 0
s s 0 0
s s 0 0
s s 0 0
Note: Bits marked with an "s" have special behavior upon reset. Refer to the user's guide supplement for this device for more details.
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19
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
System Timing
The MAXQ3100 generates its internal system clock from the external 32.768kHz crystal. This serves as the timebase for the RTC and is multiplied internally by a frequency-locked loop (FLL) to provide a system clock of 4.194MHz. Best performance is achieved when mated with a 32.768kHz crystal rated for a 6pF load. No external load capacitors are required. The frequency accuracy of a crystal-based oscillator circuit is dependent upon crystal accuracy, the match between the crystal and the oscillator capacitor load, ambient temperature, etc. A crystal warmup counter enhances operational reliability. Each time the external crystal oscillation must restart, including a power-on reset, the device initiates a crystal warmup period of approximately 2 seconds. This warmup period allows time for the crystal amplitude and frequency to stabilize before using it as a clock source. This means device operation can be slowed and power consumption minimized during periods of reduced activity. When more processing power is required, the microcontroller can increase its operating frequency. Software-selectable clock-divide operations allow flexibility, selecting whether a system clock cycle (SYSCLK) is 1, 2, 4, or 8 of the 4.194MHz oscillator cycles. By performing this function in software, a lower power state can be entered without the cost of additional hardware. For extremely power-sensitive applications, two additional low-power modes are available. * Divide-by-256 power-management mode (PMM1) (PMME = 1, CD1:0 = 00b) * Stop mode (STOP = 1) In PMM1, one system clock is 256 oscillator cycles, significantly reducing power consumption while the microcontroller functions at reduced speed. The optional switchback feature allows enabled interrupt sources, such as the external interrupts, to cause the processor to quickly exit PMM1 mode and return to a faster internal clock rate.
Power Management
Advanced power-management features minimize power consumption by dynamically matching the processing speed of the device to the required performance level.
POWER-ON RESET STOP
RWT RESET XDOG STARTUP TIMER CLK INPUT RESET DOG XDOG DONE WATCHDOG TIMER RESET WATCHDOG RESET WATCHDOG INTERRUPT
MAXQ3100
STOP GLITCH-FREE MUX CLOCK DIVIDER 32kHz CRYSTAL OSCILLATOR X32RY ENABLE CLOCK GENERATION POWER-ON RESET SYSTEM CLOCK
DIV 1 DIV 2 DIV 4 DIV 8 PWM1
INPUT FREQUENCYLOCKED LOOP ENABLE
FLLRY 4-CYCLE DELAY
SELECTOR DEFAULT
SWB SWITCHBACK SOURCE RESET STOP
WATCHDOG DONE
Figure 2. Clock Sources
20 ______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Power consumption reaches its minimum in stop mode. In this mode, the system clock and all code execution is halted. Upon receiving one of the following enabled events, the device executes a 250ms warmup delay and then begins normal operation from the point in the code following the setting of the STOP bit: * An enabled external interrupt pin is triggered. * An enabled comparator interrupt is triggered. * An external reset signal is applied to the RESET pin. * The RTC time-of-day or subsecond alarms are activated. The following peripherals can be enabled during stop mode: * Analog comparators * RTC * LCD controller * Watchdog Interrupt * * * * * * * * * External Interrupts 0 to 11 Analog Comparator 0 and 1 Interrupts Temperature Sensor Interrupt RTC Time-of-Day and Subsecond Alarms Serial Port 0 Receive and Transmit Interrupts Serial Port 1 Receive and Transmit Interrupts Timer 0 Overflow Interrupt Timer 1 Overflow and External Trigger Interrupts Timer 2 Low Compare, Low Overflow, Capture/ Compare, and Overflow Interrupts
MAXQ3100
Reset Sources
Several reset sources are provided for microcontroller control. Although code execution is halted in the reset state, the high-frequency oscillator continues to oscillate.
Interrupts
Multiple interrupt sources are available for quick response to internal and external events. The MAXQ architecture uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared within the user-interrupt routine to avoid repeated interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay, and synchronous interrupt flags require a two-instruction delay. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user program must determine whether a jump to 0000h came from a reset or interrupt source. Once software control has been transferred to the ISR, the interrupt identification register (IIR) can determine if a system register or peripheral register was the source of the interrupt. The specified module can then be interrogated for the specific interrupt source and software can take appropriate action. Because the interrupts are evaluated by user software, the user can define a unique interrupt priority scheme for each application. The following interrupt sources are available.
Power-On Reset/Brownout Reset
An internal power-on reset circuit enhances system reliability. This circuit forces the device to perform a power-on reset whenever a rising voltage on DV DD climbs above approximately V RST. Additionally, the device performs a brownout reset whenever DV DD drops below VRST, a feature that can be optionally disabled in stop mode. The following events occur during a power-on reset: * All registers and circuits enter their power-on reset state. * I/O pins revert to their reset state, with logic one states tracking DVDD. * The power-on reset flag is set to indicate the source of the reset. * Code execution begins at location 8000h following a 2-second 32.768kHz warmup.
Watchdog Timer Reset
The watchdog timer functions are described in the MAXQ Family User's Guide. Software can determine if a reset was caused by a watchdog timeout by checking the watchdog timer reset flag (WTRF) in the WDCN register. Execution resumes at location 8000h following a watchdog timer reset. Asserting the external RESET pin low causes the device to enter the reset state. The external reset functions as described in the MAXQ Family User's Guide. Execution resumes at location 8000h after the RESET pin is released.
External System Reset
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21
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
I/O Ports
The microcontroller uses the Type C and Type D bidirectional I/O ports described in the MAXQ Family User's Guide. The use of two port types allows for maximum flexibility when interfacing to external peripherals. Each port has independent, general-purpose I/O pins and three configure/control registers. Many pins support alternate functions such as timers or interrupts, which are enabled, controlled, and monitored by dedicated peripheral registers. Using the alternate function automatically converts the pin to that function. Type C port pins have Schmitt Trigger receivers and full CMOS output drivers, and can support alternate functions. The pin is either tri-stated or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. Type D port pins have Schmitt Trigger receivers and full CMOS output drivers, and can support alternate functions. The pin is either tri-stated or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. All Type D pins also have interrupt capability.
DVDD
WEAK
PD.x SF DIRECTION
MUX
DVDD
SF ENABLE
PO.x SF OUTPUT
MUX
MAXQ3100
I/O PAD PORT PIN
PI.x OR SF INPUT
FLAG
INTERRUPT FLAG
DETECT CIRCUIT
EIES.x TYPE D PORT ONLY
Figure 3. Type C/D Port Pin Schematic
22
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Real-Time Clock
A binary real-time clock keeps the time of day in absolute seconds with 1/256-second resolution. The 32-bit second counter can count up to approximately 136 years and be translated to calendar format by the application software. A time-of-day alarm and independent subsecond alarm can cause an interrupt or wake the device from stop mode. The independent subsecond alarm runs from the same RTC, and allows the application to perform periodic interrupts up to 8 seconds with a granularity of approximately 3.9ms. This creates an additional timer that can be used to measure long periods without performance degradations. Traditionally, long time periods have been measured using multiple interrupts from shorter programmable timers. Each timer interrupt required servicing, with each accompanying interruption slowing system operation. By using the RTC subsecond timer as a long-period timer, only one interrupt is needed, eliminating the performance hit associated with using a shorter timer. Higher accuracy can be obtained by using the useraccessible digital RTC trim function. This feature allows the designer to fine tune the RTC timing to compensate for crystal inaccuracies and any unintended boardlevel effects that could cause crystal-frequency drift. The user can enable a 1Hz or 512Hz square-wave output on P3.4. Frequency measurements of these signals can show if there is any deviation from the expected frequency, and writes to the RTC trim register can compensate in increments of 1 to 127 steps, with each step approximately 3.05ppm (30.5s). If the VBAT pin is not directly tied to the DVDD pin, then there may be a short increase in IDD while the device is switching between VBAT and DVDD as the RTC power source. IDD can temporarily increase up to 300A while DVDD is rising and in the range 1.05 x VBAT < DVDD < [(1.05 x V BAT ) + 200mV]. A similar effect may be observed while VBAT is falling and in the range [(0.95 x DVDD) - 200mV] < VBAT < 0.95 x DVDD.
Timer 0
The timer 0 peripheral includes the following: * 8-bit autoreload timer/counter * 13-bit or 16-bit timer/counter * Dual 8-bit timer/counter * External pulse counter
MAXQ3100
Timer 1
The timer 1 peripheral includes the following: * 16-bit autoreload timer/counter * 16-bit capture * 16-bit counter * Clock generation output
Timer 2
The timer 2 peripheral includes the following: * 16-bit autoreload timer/counter * 16-bit capture * 16-bit counter * 8-bit capture and 8-bit timer * 8-bit counter and 8-bit timer * Infrared carrier generation support
Watchdog Timer
An internal watchdog timer greatly increases system reliability. The timer resets the processor if software execution is disturbed. The watchdog timer is a freerunning counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of four programmable intervals ranging from 212 to 221 system clocks in its default mode, allowing flexibility to support different types of applications. The interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. At 4.194MHz, watchdog timeout periods can be programmed from 976s to 128s, depending on the system clock mode.
23
Programmable Timers
The MAXQ3100 incorporates one instance each of the timer 0, timer 1, and timer 2 peripherals. These timers can be used in counter/timer/capture/compare/PWM functions, allowing precise control of internal and external events. Timer 2 supports optional single-shot, external gating, and polarity control options as well as carrier generation support for infrared transmit/receive functions using serial port 0.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
In-Circuit Debug
Embedded debugging capability is available through the debug port TAP. Embedded debug hardware and embedded ROM firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. Figure 4 shows a block diagram of the in-circuit debugger. The in-circuit debug features include: * Hardware debug engine * Set of registers able to set breakpoints on register, code, or data accesses * Set of debug service routines stored in the utility ROM The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug engine can monitor internal activities and interact with selected internal registers while the CPU is executing user code. Collectively, the hardware and software features allow two basic modes of in-circuit debugging: * Background mode allows the host to configure and set up the in-circuit debugger while the CPU continues to execute the application software at full speed. Debug mode can be invoked from background mode. * Debug mode allows the debug engine to take control of the CPU, providing read/write access to internal registers and memory, and single-step trace operation.
DEBUG SERVICE ROUTINES (UTILITY ROM)
MAXQ3100
CPU DEBUG ENGINE TMS TCK TDI TDO TAP CONTROLLER CONTROL BREAKPOINT ADDRESS DATA
Figure 4. In-Circuit Debugger
Serial Peripherals
The MAXQ3100 incorporates two 8051-style universal synchronous/asynchronous receiver/transmitters. The USARTs allow the device to conveniently communicate with other RS-232 interface-enabled devices, as well as PCs and serial modems when paired with an external RS-232 line driver/receiver. The dual independent USARTs can communicate simultaneously at different baud rates with two separate peripherals. The USART can detect framing errors and indicate the condition through a user-accessible software bit.
MODE Mode 0 Mode 1 Mode 2 Mode 3 TYPE Synchronous Asynchronous Asynchronous Asynchronous START BITS -- 1 1 1
The time base of the serial ports is derived from either a division of the system clock or the dedicated baud clock generator. The following table summarizes the operating characteristics as well as the maximum baud rate of each mode. Serial port 0 contains additional functionality to support low-speed infrared transmission in combination with the PWM function of timer 2. When enabled in this mode, the serial port automatically outputs a waveform generated by combining the normal serial port output waveform with the PWM carrier waveform output by timer 2, using a logical OR or logical NOR function. The output of serial port 0 in this mode can be used to drive an infrared LED to communicate using a fixed-frequency carrier modulated signal. Depending on the drive strength required, the output may require a buffer when used for this purpose.
DATA BITS 8 8 8+1 8+1
STOP BIT -- 1 1 1
MAX BAUD RATE AT 4.194MHz 1.05Mbps 131kbps 131kbps 131kbps
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Analog Comparators
The MAXQ3100 incorporates a pair of 1-bit analog-todigital comparators. The comparator inputs can be connected to a wide range of peripherals, including chemical, motion, or proximity detectors; voltage-supply monitoring; or any other appropriate analog input. The comparator measures the analog inputs against the internal +1.25V reference. The polarity of the internal comparator-output signal can be selected to indicate a value above or below the internal reference. The comparators can be configured to generate an optional interrupt in addition to setting an internal flag when the input is out of range. A combination of the two comparators along with appropriate biasing of an input allows the two comparators to be used as a window comparator. When not in use, the pins associated with the comparator are usable as general-purpose I/O. A useful feature of the comparators is that they can be used to wake the device from stop mode, allowing the device to monitor external voltages while in an ultralow-power mode and only wake when necessary. polled by software, or, optionally, the temperature conversion complete interrupt can be used to alert the system that the results are ready to be read from the temperature results register (TEMPR).
MAXQ3100
Applications Information
Grounds and Bypassing
Careful PC-board layout significantly minimizes crosstalk among the comparator inputs and other digital signals. Keep digital and analog lines separate, and use ground traces as shields between them where possible. Bypass DVDD with a capacitor as low as 1F and keep bypass capacitor leads short for best noise rejection. This device incorporates both analog and digital components, straddling both the analog and digital ground planes. For increased accuracy, an LC filter can be used to isolate pin 59. This pin powers the analog circuitry, and the additional filtering reduces the noise entering the analog block.
Device Applications
The low-power, high-performance RISC architecture of the MAXQ3100 makes it an excellent fit for many applications that require analog measurements combined with the intelligence of a full-featured microcontroller. Simple voltage-dividers can be used to scale any input into a value in the range of the +1.25V reference. The dual comparators allow the device to function as a simple limit comparator or window comparator in a wide range of analog applications.
Temperature Sensor
The internal temperature sensor has a user-selectable resolution of 10 (0.5C), 11 (0.25C), 12 (0.125C), or 13 (0.0625C) bits. Higher resolutions require longer conversion times. Setting the START bit initiates the temperature conversion, and the temperature sensor hardware clears the bit when the conversion is complete. This bit can be
CMON
INTERNAL 1.25V REFERENCE
CMO CMF
CMPOL Q CMPx SET CMM CMM INTERRUPT REQUEST
Figure 5. Analog Comparator Functional Diagram
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25
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Additional Documentation
Designers must have four documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about programming, device features, and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers. * The MAXQ3100 data sheet, which contains electrical/timing specifications and pin descriptions, available at www.maxim-ic.com/MAXQ3100. * The MAXQ3100 errata sheet, available at www.maxim-ic.com/errata. * The MAXQ Family User's Guide, which contains detailed information on core features and operation, including programming, avaliable at www.maximic.com/MAXQUG. * The MAXQ Family User's Guide: MAXQ3100 Supplement, which contains detailed information on features specific to the MAXQ3100, available at www.maxim-ic.com/MAXQ3100UG.
Development and Technical Support
A variety of highly versatile, affordably priced development tools for this microcontroller are available from Maxim/Dallas Semiconductor and third-party suppliers, including: * Compilers * In-circuit emulators * Integrated development environments (IDEs) * JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found on our website at www.maxim-ic.com/microcontrollers. Technical support is available through email at maxq.support@dalsemi.com.
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Typical Application Circuits
Typical Application Circuit #1
Typical Application Circuit #1 shows a general-purpose implementation using a MAXQ3100 that reads two sensor inputs, displays result and status information on an
LCD display, and also interfaces simultaneously with an RS-232 and RS-485 networks. I/O pins that are not dedicated to special functions are available to control other system functions.
MAXQ3100
3.3V
DVDD
MAXQ3100
DIRECT INPUT FROM USERDEFINED SENSOR
TXD0 RXD0
RS-232 Tx/Rx
CMP0 TXD1 RS-485 Tx/Rx RXD1 VREF Px.x CMP1
R1
SCALED COMPARATOR INPUT
RTS
R2 BACKUP BATTERY VBAT COM[3:0] NOTE THAT UP TO 160 LCD SEGMENTS CAN BE DRIVEN IF OTHER MUXED PIN FUNCTIONS ARE NOT USED. I2C FRAM OR EEPROM P2.3 P2.2 GENERALPURPOSE I/O TDO JTAG DOWNLOAD/ DEBUG CONNECTOR TDI TCK TMS 32KIN INT6 INT7 BUTTON 1 BUTTON 2 LCD MODULE SEG[39:0]
32KOUT
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27
Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Typical Application Circuits (continued)
Typical Application Circuit #2
Another target application of the MAXQ3100 is in the electricity metering market. When coupled with an analog front-end, the microcontroller becomes the core of an affordable electricity metering solution. Such an application can accurately keep time, incorporate a versatile display, and allow for multiple modes of communication. See Typical Application Circuit #2.
UNREGULATED SUPPLY
REGULATOR 3.3V
DVDD
IR Tx/Rx CIRCUIT
MAXQ3100
CMP0 VREF VBAT CMP1 RXD0 IR Rx MODULE TXD0
BACKUP BATTERY
ENERGY METERING IC CALIBRATION EQUIPMENT
I
L SO
AT
IO
N
T0 TXD1 SQW RXD1 RS-232 Tx/Rx
I2C FRAM OR EEPROM
P2.3 P2.2 LCD MODULE SEG[39:0] COM[3:0] TDO NOTE THAT UP TO 160 LCD SEGMENTS CAN BE DRIVEN IF OTHER MUXED PIN FUNCTIONS ARE NOT USED.
JTAG DOWNLOAD/ DEBUG CONNECTOR
TDI TCK TMS 32KIN INT7 INT6 32KOUT
BUTTON 1 BUTTON 2
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC
Pin Configuration
78 P0.1/INT1/RXD0 79 P0.2/INT2/T0G 80 P0.3/INT3/T0 77 P0.0/INT0/TXD0
MAXQ3100
70 P3.6/CMP1
69 P3.5/CMP0
68 P3.4/SQW
67 P3.3/TMS
DGND P0.4/INT4/T1 P0.5/INT5/T1EX P0.6/INT6 P0.7/INT7 DVDD COM0 COM1 COM2 COM3 DGND SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12
72 VBAT
71 RESET
75 DGND
73 32KIN
76 DVDD
TOP VIEW
66 P3.2/TCK
65 P3.1/TDO 64 63 62 61 60 59 58 57 56 55 54 53
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 31 25 26 28 29 32 33 34 35 36 38 27 37 39 40
74 32KOUT
P3.0/TDI P1.3/INT11/RXD1 P1.2/INT10/TXD1 P1.1/INTP/T2A P1.0/INT8/T2B DVDD DGND VADJ VLCD2 VLCD1 VLCD DVDD DGND P2.7/SEG39 P2.6/SEG38 P2.5/SEG37 P2.4/SEG36 P2.3/SEG35 P2.2/SEG34 P2.1/SEG33 P2.0/SEG32 SEG31 SEG30 SEG29
MAXQ3100
52 51 50 49 48 47 46 45 44 43 42 41
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
MQFP
______________________________________________________________________________________
SEG26
SEG27
SEG28
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Mixed-Signal Microcontroller with Analog Comparators, LCD, and RTC MAXQ3100
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo).
Revision History
Rev 0; 6/07: Original release.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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